[1] Elspas B.: The theory of autonomous linear sequential networks. IRE Trans. CT-6 (1959, March), 1, 45-60.
[2] Gill A.:
Analysis of linear sequential circuits by confluence sets. IEEE Trans. EC-13 (1964, June), 3, 226-231.
MR 0175700 |
Zbl 0133.09901
[3] Green J. H., San Soucie R. L.: An error correcting encoder and decoder of high efflciency. Proc. IRE 46, 1741-1744.
[4] Gruder J. F., Perlman M.: A feedback shift-register scaler. IEEE Trans. Comm. and Electr. (1964, Nov.), 6, 745-752.
[5] Huffman D. A.:
The synthesis of linear sequential coding networks. In Information Theory (ed. C. Cherry), Acad. Press, New York 1956.
Zbl 0152.35702
[6] Мишина А. П., Проскуряков И. В.:
Высшая алгебра (СМБ). Наука, Москва 1965.
Zbl 1225.00032
[7] Peterson W. W.:
Error-correcting codes. J. Wiley, 1961, New York (ruský překlad: Коды, исправляющие оюибки. Мир, Москва 1964).
MR 0121260 |
Zbl 0105.32802
[8] Roth H. H.: Linear binary shift register circuits utilizing a minimum number of mod-2 adders. IEEE Trans. IT-11 (1965, April), 2, 215-220.
[9] Sholefield P. H. R.: Shift registers generating maximal length sequences. Electr. Technology 37 (1960, Oct.), 10, 389-394.